The present invention relates to a large-scale integrated circuit device and, more particularly, to a technique which may be effectively applied, for example, to a wafer scale memory or the like.
There is one type of large-scale integrated circuit device, for example, a wafer scale memory, which comprises a plurality of unit integrated circuits formed on the same wafer. In this type of large-scale integrated circuit device, a plurality of unit integrated circuits mounted thereon are selectively validated after the normality thereof has been confirmed by a given functional test.
Large-scale integrated circuit devices such as wafer scale memories are mentioned in British Patent laid-open publication numbers GB1377859, GB1525048, GB2173946, GB2174518, GB2177825 and GB2178204. Future trends in wafer scale integration are mentioned in PROCEEDINGS OF THE IEEE, VOL. 74, NO. 12, December 1986, p. 1741-p. 1752. A method of coupling unit integrated circuits by a logic switching circuit is mentioned in ELECTRONICS & POWER, April 1986, p. 283-p. 285. A method of relieving defects in a wafer scale memory is mentioned in Japanese Patent Laid-Open No. 63-266700 (laid open on Nov. 2, 1988).